1. Field of the Invention
The present invention is directed to a method of determining electrical properties of silicon-on-insulator wafers. More specifically, the present invention is drawn to a method of determining silicon-on-insulator wafer electrical properties by measuring electrical properties of the silicon-on-insulator between two electrodes and analyzing resulting electrical properties after imposing a voltage thereon.
2. Background of the Prior Art
Silicon-on-insulator (SOI) starting substrate material can be used as an alternative to standard silicon wafers (xe2x80x9cbulk siliconxe2x80x9d) to produce integrated circuits. Quality control of starting SOI wafers is necessary because such wafers are produced in xe2x80x9cbatchxe2x80x9d processes which can have variability in defect densities, interface perfection, and contamination. The electrical properties, such as electron and hole mobilities, surface state densities, fixed charge densities, and surface scattering properties, in part determine how well a field effect transistor (FET) will perform when this starting material is processed into integrated circuits. One method for assessing these starting wafer properties is to build FETs in the material using standard device processes like ion implantation, annealing, oxidation or diffusion, which are costly and time consuming. An alternative is to use the buried oxide in the SOI structure as a gate oxide, place two electrodes on the Si surface as source and drain contacts, and use this as a xe2x80x9cpseudo-FET.xe2x80x9d Electrical measurements using such pseudo-FETs have been described in, for example, IEEE Electron Device Letters, Vol 13, pg 102, 1992 and in Electrical Characterization of Silicon-on-Insulator Materials and Devices, Kluwer Academic Publishers, Boston, 1995. Similar measurements made using mercury electrodes have been described in Proc. 1997 IEEE International SOI Conference, pg 180, and in Electrochemical and Solid State Letters, 2, 242, 1999). However, all this prior art fails to present details on how these test structures are best made, how to account for the parasitic effects which limit their usefulness and how to set the correct voltage conditions for correct measurements. Moreover, these references do not present a complete mathematical analysis needed to obtain electrical properties.
A new method has now been developed for providing electrical properties of silicon-on-insulator wafers which accounts for parasitic effects, sets the correct voltage conditions for correct measurement and, in summary, provides means for obtaining electrical properties of the SOI wafer.
An electrical test structure of the present invention is made by depositing a doping metal, such as aluminum, to provide an Al/Si interface, on the back of a SOI wafer, heat treating the wafer to convert the Al/Si interface to an ohmic contact, masking a mesa on the top Si surface, removing the Si layer outside of this masked mesa, treating the remaining Si surface in an etchant, contacting this surface with two or more mercury electrodes to act as source and drain of a FET, applying voltages between the source and drain, applying a second voltage between the bottom aluminum layer and the source electrode, and varying these voltages appropriately to obtain field effect transistor current-voltage behavior, choosing the correct voltage range depending on the thicknesses of the Si and buried oxide layers, repeating the measurements at several time periods until steady state behavior is obtained, applying mathematical analysis to the data in order to extract the electrical parameters and correcting for parasitic effects and other measurement variability. Liquid metals other than mercury, such as gallium mixed with indium, tin or combinations of mercury with other metals such that the mixture is liquid at room temperature may also be used. Alternatively, metals such as Al, Ag, Au, Sn, and others may be evaporated onto the Si surface to act as source and drain electrodes in solid rather than liquid form.